With development of integrated circuits, power consumption is becoming one important performance index. As a basic unit of an integrated circuit, a field effect transistor having superior performance and low power consumption has been sought. Due to introduction of dual-gate and tri-gate structures as well as techniques with high-k materials and stress silicon, the performances of field effect transistors have been significantly improved. However, a sub-threshold slope of a conventional field effect transistor is not less than ln 10·kT/q on account of limit caused by drift and diffusion, resulting in great difficulties in reduction of power supply voltage and the channel length under identical characteristics. A main solution to break this limit is a PN junction-based tunneling field effect transistor which has attracted wide attention because of its low power consumption and low sub-threshold slope.
In a conventional tunneling field effect transistor, a P (hole-doping) region and an N (electron-doping) region could be formed respectively at the source and drain terminals, and intrinsic material could be used at the intermediate channel. The electron hole could be tunneling transferred from the P region to the N region by a drive voltage, forming tunneling current. Since the conventional tunneling field effect transistor could generate current by tunneling effect, its on-state current may be smaller than that of a conventional field effect transistor having thermal emission mechanism.